1. Field of the Invention
This invention relates to current feedback amplifiers. More particularly, this invention relates to circuitry to eliminate the peaking of gain at high frequencies due to parasitic capacitance at the negative, or inverting input terminal of a current feedback amplifier as well as to eliminate bias current variations at the negative input terminal.
2. Description of the Related Art
FIG. 1 shows a conventional current feedback amplifier circuit. The circuitry includes an input stage formed by two complementary buffers including four transistors 101-104 along with two current mirrors 120 and 130. The circuitry further includes an output stage formed by output buffer 140. Feedback for the amplifier is provided by an external feedback resistor R.sub.F, while gain is controlled by an external resistor R.sub.G and compensation is provided by capacitor C.sub.COMP.
In the input stage, a first buffer of the two complementary buffers is provided by a pair of complementary transistors 101 and 102. The bases of transistors 101 and 102 are connected to serve as a positive input terminal V.sub.IN+ for the amplifier. The collector of transistor 101 is connected to a negative power supply V-, while the collector of transistor 102 is connected to a positive power supply V+. Transistors 101, 102 are biased into conduction by two current sources 106, 108. The first current source 106 is connected between the positive power supply V+ and the emitter of transistor 101. The second current source 108 is connected between the negative power supply V- and the emitter of transistor 102.
The second buffer of the input stage is provided by a second pair of complementary transistors 103 and 104. Transistors 103 and 104 each have a base connected to an emitter of a complementary transistor in the first buffer. The second pair of transistors 103, 104 are connected in an emitter follower configuration with common emitters being connected at a negative, or inverting input terminal V.sub.IN-.
The current mirrors 120 and 130 of the input stage have inputs I.sub.IN connected to respective collectors of the second pair of transistors 103, 104. The outputs I.sub.OUT of current mirrors 120, 130 are connected to form a gain node G. Current mirror 120 includes two pnp type transistors 122 and 124 with common bases, while current mirror 130 includes two npn type transistors 132 and 134 with common bases. Transistors 122 and 124 each have emitters connected through an emitter resistor to the positive power supply V+, while transistors 132 and 134 have emitters connected through an emitter resistor to the negative power supply V-. Transistors 122 and 132 each have a base to collector connection. The collectors of transistors 122 and 132 form the input I.sub.IN of respective current mirrors 120 and 130. Transistors 124 and 134 have collectors forming the output I.sub.OUT of respective current mirrors 120 and 130. Although specific circuitry for current mirrors 120 and 130 is shown, current mirrors 120 and 130 can be made up of other current mirror circuitry known in the art.
The output buffer 140 shown includes four transistors 141-144 connected as a pair of complementary buffers and biased by current sources 146 and 148 similar to the complementary buffers formed by transistors 101-104 as biased by current sources 106 and 108 in the input stage. The output buffer 140 is connected between gain node G and the amplifier output terminal V.sub.OUT. Although specific circuitry is shown for output buffer 140, other circuitry for output buffer 140 known in the art can be utilized which provides a high impedance at gain node G.
The feedback resistor R.sub.F is connected between the amplifier output terminal V.sub.OUT and the negative input terminal V.sub.IN- to provide the current feedback for the amplifier. The external resistor R.sub.G connected from the negative input terminal V.sub.IN- to ground controls amplifier gain.
C.sub.IN is not intentionally connected, but is a parasitic capacitance from V.sub.IN- to ground. C.sub.IN arises from the parasitic capacitance associated with amplifier construction and the bodies of R.sub.F and R.sub.G. Compensation capacitor C.sub.COMP is intentionally connected from the high capacitance gain node G to ground to control the gain vs. frequency characteristics of the amplifier.
In operation, the two complementary buffers formed by transistors 101-104 buffer the voltage at the positive input terminal V.sub.IN+ and present it to the negative input terminal V.sub.IN-. An error current is provided at the negative input terminal V.sub.IN- by resistors R.sub.F and R.sub.G which form a voltage divider feedback circuit to divide the voltage at the amplifier output terminal V.sub.OUT. The divided voltage is the voltage that would exist at V.sub.IN- if V.sub.IN- were disconnected from the gain node G, or V.sub.OUT R.sub.G /(R.sub.G +R.sub.F).
For a given output voltage at V.sub.OUT, the error current flows into or out of the feedback circuit through the negative input terminal V.sub.IN- when the voltage at V.sub.IN- deviates from the divided voltage, V.sub.OUT R.sub.G /(R.sub.G +R.sub.F). The error current is shared, or split by the emitters of transistors 103 and 104. The error current passes from the emitters through the collector of transistors 103 and 104. Current mirror 120 mirrors the current flowing in the collector of transistor 103 and sources the mirrored current to gain node G. Current mirror 130 sinks a replica of the current flowing in the collector of transistor 104 from gain node G. Current mirrors 120 and 130, thus, rejoin the error current halves into the gain node G to apply to the input of output buffer 140.
Error current continues to flow until V.sub.OUT =V.sub.IN- (R.sub.F +R.sub.G)/R.sub.G at which time the error current falls to zero. With no error current flowing into or out of the feedback circuit through node V.sub.IN-, the collector currents in transistors 103 and 104 are equal and the current sourced by the current mirror 120 equals the current sunk by the current mirror 130. As a result, the net current into the gain node G is zero and the voltage applied to the input of output buffer 140 remains unchanged.
With the feedback divider provided by resistors R.sub.F and R.sub.G, the amplifier gain is V.sub.OUT /V.sub.IN- or (R.sub.F +R.sub.G)/R.sub.G. With increasing frequency, capacitances have an increasing effect on gain. Compensation capacitor C.sub.COMP is provided to dominate other capacitances in the circuitry to control the amplifier gain characteristics with increasing frequency as shown by curve 202 of FIG. 2. With C.sub.COMP, gain drops to the 3 dB bandwidth point at f=1/(2.pi.C.sub.COMP R.sub.F) as shown.
As increased bandwidth is desired, C.sub.COMP is reduced toward the value of C.sub.IN. With C.sub.COMP approaching C.sub.IN, however, C.sub.IN begins to affect the amplifier output causing undesirable gain peaking beyond the expected 3 dB bandwidth of 1/(2.pi.C.sub.COMP R.sub.F) as shown by curve 204 in FIG. 2.
It is thus desirable to reduce C.sub.IN. In practice it has not been possible to reduce C.sub.IN below about 1.2 pF with surface mount construction or below about 2.5 pF with DIP and leaded components.